1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device used as a differential amplifier circuit for amplifying an output of a sense amplifier, etc.
2. Description of the Related Art
It is usually difficult to form capacitors in an integrated circuit (IC) due to limited space. To deal with this, a direct-coupled circuit is frequently used, however, this circuit has a problem of drift. To solve this problem, a differential amplifier circuit having a pair of transistors is used. The differential amplifier circuit is required to operate at high speed, consume less electric power, and have a large power source and a large temperature margin.
FIG. 1 shows a conventional semiconductor integrated circuit device serving as a differential amplifier circuit. This circuit is interposed between, for example, a sense amplifier of a semiconductor memory and an output buffer circuit, to amplify an output level of the sense amplifier and provide it to the output buffer circuit.
In FIG. 1, numerals 1 and 2 denote NMOS transistors for receiving input signals, and 3 and 4 denote PMOS transistors that are cross-connected with the NMOS transistors 1 and 2. Nodes 21 and 22 provide output signals. Gates of the NMOS transistors 1 and 2 receive binary digital input signals IN1 and IN2, respectively. These input signals are inverted relative to each other. Sources of the NMOS transistors 1 and 2 are connected to a ground, i.e., a low-potential power source Vss.
The input signals IN1 and IN2 form binary levels between, for example, 4 V and 3.1 V. When the signal IN1 is High (H), the NMOS transistor 1 is turned ON to set the node 21 to Low (L), e.g., 0 V. This level L is applied to the gate of the PMOS transistor 4 to turn ON the PMOS transistor 4, thereby setting the node 22 to H, e.g., Vcc=5 V. In this way, the levels of the input signals IN1 and IN2 are amplified between 0 V and Vcc, and supplied from the nodes 21 and 22 to the outside. When the input signal IN1 is L, an operation opposite to the above will take place.
The conventional semiconductor integrated circuit device mentioned above may realize a certain amount of high-speed operation and low power consumption but must be further improved to achieve a speedier operation.
Using MOS transistors may be advantageous in reducing power consumption but restrict operation speeds. There is room, therefore, to utilize high-speed characteristics of other active elements such as bipolar transistors.